Performance and energy consumption behavior of embedded applications are increasingly being dependent on their memory usage and memory access patterns. In this talk I will overview an integer linear programming (ILP) based solution to the combined problem of memory hierarchy design and data allocation. The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining the optimal on-chip memory partitioning across processors and data allocations across memory components. I will then explain a latency-aware Scratch Pad Memory (SPM) space management technique that utilizes parameter variations. Large variability in circuit delay occurs in scaled technologies as a result of process parameter variations. This delay or latency variation problem is particularly pressing for memory components due to the minimum sized transistors used to build them. Current memory design techniques mostly cope with such variations by adopting a worst-case design option. Instead of operating under the worst-case design option, we propose a compiler-driven approach that operates with different latencies for the different SPM lines.

DATE: 29 March, 2007, Thursday@ 13:40
PLACE: EA 409